The present invention relates to a semiconductor wafer having an accurately aligned SOI (Silicon-On-Insulator) structure, and a method of producing the same.
Today, to meet the increasing demand for fine and dense semiconductor IC (Integrated Circuit) configurations, a laminate integration of devices, wirings and so forth is under study. An SOI structure is attracting increasing attention as one of laminate integration technologies relating to semiconductor wafers. In the SOI structure, a layer of silicon oxide or similar dielectric substance is implemented as a buried layer, and a thin film of single-crystal silicon is formed on the buried layer. The prerequisite with the SOI structure is that an SOI layer be aligned with the buried layer at the time of the first patterning of the SOI layer. This is particularly true when a pattern corresponding to devices is provided on the surface of the SOI layer. However, the problem is that the buried layer underlies the SOI layer and cannot be observed with visible rays. Means for observing the buried structure has been proposed in various forms in the past. Japanese Patent Laid-Open Publication No. 2-312220, for example, teaches an aligning device using a transmission image formed by infrared rays. This aligning device aligns a plurality of wafers formed with two or more device layers.
However, the above aligning device has a problem that undesirable contrast occurs in addition to the infrared transmission image representative of the buried layer. The undesirable contract is superimposed on the desired image and prevents the pattern of the aligning oxide film from being clearly observed. This lowers the alignment accuracy and brings about defective characteristic due to misalignment.